In digital telecommunications networks, in particular, PCM t.d.m. telecommunications networks in which pulse train oscillators are connected at the network nodes, one of the aims is to compensate for bit frequency differences between signals transmitted on various digital telecommunications lines leading to a network node, i.e., transmitted from various directions. Compensation for these differences is necessary for a satisfactory switch-through of telecommunications signals. Various methods for accomplishing compensation for bit frequency differences are known (see Proc. IEE, 113 (1966) 9, 1420 . . . 1428 1421; Informationen Fernsprech-Vermittlungstechnik 5 (1969), 1, 48 . . . 59, 51; NTF 42 (1972), 297 . . . 310).
The first method is known as the asynchronous process in which each PCM t.d.m. exchange in a PCM t.d.m. telecommunications network possesses its own independent pulse generator. Accordingly, each receiving t.d.m. line opens into a so-called full store, the storage capacity of which corresponds to the number of bits in each pulse frame. The received binary words are stored in the full store until they fit into the pulse frame of the relevant PCM t.d.m. exchange, thereby simultaneously effecting a so-called frame compensation.
Another method is the quasi-synchronous process or so-called blind bit process in which the PCM t.d.m. exchanges of a PCM t.d.m. telecommunications network posses their own independent pulse generators, but the information bit frequency, i.e., the average number of information bearing bits per second, is rendered the same for all the PCM t.d.m. exchanges of the entire PCM t.d.m. telecommunications network. The differences which occur between the bit pulse train frequencies of the individual PCM t.d.m. exchanges and the uniform information bit frequency are compensated for by the insertion of so-called blind bits which are information free.
Other methods are also known for bit frequency compensation. In the servo-synchronous process also known as the homochronous process or the master slave process, a central pulse generator determines the bit frequency of the individual PCM t.d.m. exchanges of a PCM t.d.m. telecommunications network. Finally, in the autosynchronous process, the individual PCM t.d.m. exchanges posses individual pulse generators which are dependent on each other for mutual synchronization. For example, mutal synchronization is accomplished in accordance with the so-called phase averaging principle.
To this end, in a known manner, the t.d.m. lines incoming in the individual network nodes (exchanges or link regenerators) of a PCM t.d.m. telecommunications network are assigned line-individual phase discriminators. The inputs of these phase discriminators are each fed with a pulse sequence corresponding to the relevant line bit pulse train and with a pulse sequence corresponding to the exchange bit pulse train of the relevant network node. The output signals, which correspond to the particular phase shift between the relevant line pulse train and the exchange pulse train, combined via a sum or mean value forming element, form the regulating signal for the frequency regulation of the exchange pulse train oscillator. The above phase shift can be caused by different pulse train frequencies in the pulse train oscillators provided in the individual network nodes of the telecommunications network and/or by changes in line transit times. In this connection, it is well known (see ECJ 49 (1966) 11, 165) to use a pulse sequence corresponding to the relevant line bit pulse train or exchange bit pulse train with a pulse repetition frequency which is a sub multiple of the bit pulse train frequency. This can be accomplished in a manner (see NTZ 23 (1970) 5, 257 . . . 261) which enables the use of pulse train extractors of flywheel circuits (a flywheel circuit is shown in FIG. 5 of the U.S. Pat. No. 3,483,330) on incoming PCM t.d.m. lines in the individual exchanges of a PCM t.d.m. telecommunications network. The line bit pulse trains of the individual incoming PCM t.d.m. lines are then obtained from the received PCM signals. The phase shifts of these line bit pulse trains are related to the exchange bit pulse train of the relevant exchange which regulates the pulse train oscillator supplying this exchange bit pulse train. The line bit pulse train and exchange bit pulse train are conducted to two pulse frequency reducers which commence the frequency reduction preferably displaced by 180.degree. in relation to one another (reference phase new formation). A phase comparison is then effected between the output pulse sequences with the aid of a phase discriminator individually assigned to the lines in the form of a bistable trigger circuit. Because the d.c. mean value of the output signal of this trigger stage is (in a periodic function) proportional to the phase difference, it is thus proportional to the integral of the frequency difference, namely the difference between line pulse train frequency and exchange pulse train frequency. The output signals of all the trigger circuits assigned individually to the lines are added to form a mean value via generally identical resistors and are smoothed via an RC element. The capacitor voltage can then adjust the pulse train frequency of the exchange pulse train oscillator via a capacitance diode. The resetting flank of the exchange pulse train frequency reducer in each case upon the upon so-called counting input of the individual trigger circuits; if a line pulse train breaks down, the associated trigger circuit operates as counter with a pulse interval ratio of 1:1. A regulating voltage is generated which corresponds to the identity of line pulse train frequency and exchange pulse train frequency.
It is also possible to use a plurality of the above methods and principles simultaneously. Thus, it is well known (see NTF 42 (1972) p. 306 and 307; German Pat. No. 1,766,477 = VPA 68/2479) that, in the individual network levels of a telecommunications network comprising a plurality of network levels and in the individual networks of a telecommunications network comprising a plurality of networks a mutual synchronization of the pulse train oscillators may be accomplished in accordance with the auto-synchronous process and direct synchronization may be accomplished between the various network levels and between the individual telecommunications networks via a plurality of supply lines in accordance with the servo-synchronous process.
Phase differences can also be determined with the aid of discriminators (see German AS 1,949,417 = VPA 69/2951) each of which possess logic-linking circuits provided with two inputs and one input. In each of these discriminators, one input is connected to the output of the particular line pulse train frequency reducer and the other input is connected to the output of the exchange pulse train frequency reducer. The output signals are linked via a sum- and mean value- circuit.
The operative characteristic of known phase discriminators, i.e., the dependence of the output signals on the phase differences in the input pulse sequences, is generally a 2.pi. periodic function which increases within a 2.pi. and a .+-..pi. range. It is stipulated that the pulse repetition frequency of the pulse sequences corresponding to the relevant line bit pulse train and exchange bit pulse train are subjected to the actual phase difference determination to the extent that their pulse repetition frequency represents a sub multiple of the bit pulse train frequency. Accordingly, it is endeavoured (see also ECJ 49 (1966) 11, 168) to ensure that phase differences are detected in the course of the frequency regulation process without the need for the discriminator operative point to depart from its original 2.pi. (or .+-..pi.) operative range. These phase differences are caused by both the existing frequency tolerances in the pulse train oscillators arranged in the network nodes (exchanges or link regenerators) of the t.d.m. telecommunications network and the expected transit time fluctuations on the t.d.m. lines connecting the network nodes in the t.d.m. telecommunications network.
Nevertheless, it is never possible to entirely rule out the possibility that the discriminator operative point will move away from the original 2.pi. (or .+-..pi.) range due to special circumstances. This can occur, for example, on account of a sufficient difference between the exchange pulse train frequencies of the exchange pulse train oscillator in a network node of a digital telecommunications network and an oscillator by which it is being externally synchronized. For example, the external oscillator may be located in a network node of a superordinated telecommunications network or a newly connected network node in one and the same digital telecommunications network. In such a case, the periodic curve for a discriminator or frequency regulator shows an extension of the build up time in which the synchronization is achieved, and in a reduction in the pull in range.
Circuit arrangements have been developed which have endeavored to reduce these undesired operating characteristics. For example, it is well known to adjust the frequency of an oscillator whose frequency can be altered in dependence upon a d.c. voltage within specific limits to an externally supplied frequency, where the externally supplied frequency and the frequency emitted from the oscillator are conducted to a phase comparison circuit. This phase comparison circuit emits a d.c. voltage fundamentally proportional to the frequency difference which is fed via a low pass filter to the oscillator for the purpose of frequency adjustment. In such circuits, an additional circuit arm is provided which when an extreme value of the voltage emitted from the phase comparator circuit is reached, stores this extreme value and conducts it to the oscillator until the latter has been regulated in its frequency to such an extent that the voltage emitted from the phase comparator circuit falls below its extreme value (see German OS 1,804,813). Here the phase comparator circuit is in the form of a bistable trigger circuit which, in dependency on whether the pulse arriving therein belongs to the pulse series which has been supplied from the exterior or has been emitted by the oscillator, emits two different voltages. Further bistable trigger stages are provided which control AND circuits for feeding the pulses to the phase comparator circuit in such manner that on the occurrence of a given phase difference between the pulses, the pulses are not permitted to pass. Two transit time elements whose transit time corresponds to the width of a pulse are arranged in such a way that further AND circuits are alternatively blocked or opened in dependence upon the phase difference between the pulses and/or delayed pulses of the other pulse series. The outputs of the further AND circuits are each connected to one input of the further bistable trigger stages. This known circuit arrangement has several disadvantages. On the one hand, this circuit is unable to rediscover its original .+-..pi. operative range once the phase difference has exceeded a guantity of 3.pi.; on the other hand, by the particular dimensioning of the transit time elements, it is limited to a specific width of the timing pulses which, at least in the case of long lines, requires the provision of additional pulse shapers.
Another known circuit arrangement (see Herold "Synchronization digitaler Fernmeldenetze durch Phasenmittelung mit Stellgroessenuebertragung" Dissertation TU Munich 31.1./2.3.1972, p. 112) exhibiting a discriminator operative curve possessing a constant range on both sides of a linear range, and which is referred to as quasi-linear, has, in addition to the actual phase discriminator in the form of a bistable trigger circuit, an additional phase comparison circuit. When the thresholds +.pi., +3.pi., +5.pi. . . . -.pi., -3.pi. , - 5.pi. are exceeded, it emits a positive or negative pulse, where the number of the pulses is converted in a digital analog converter into a corresponding voltage. At the instant of switch on, this voltage is equal to zero. After a specific number of positive pulses, this voltage has a specific positive value and, only after the same number of negative pulses, again becomes zero (likewise for negative pulses). This voltage is fed to two threshold value circuits which, when they respond, block the one or the other input of the bistable trigger circuit so that the output signal remains at one of its two output values. This known circuit arrangement avoids the shortcomings of the previously mentioned circuit arrangement. However, it employs an analog technique which on the one hand requires a corresponding outlay in the form of a digital analog converter and on the other hand entails corresponding inaccuracies in respect of the threshold value elements based on the continuously finite width of the response thresholds.